-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"

-- DATE "11/25/2023 13:15:20"

-- 
-- Device: Altera EP4CE6E22C8 Package TQFP144
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	lab2_fre_div3_021 IS
    PORT (
	B2_021 : OUT std_logic;
	S : IN std_logic_vector(1 DOWNTO 0);
	C_1KHZ_021 : IN std_logic;
	D_500HZ_021 : IN std_logic
	);
END lab2_fre_div3_021;

-- Design Ports Information
-- B2_021	=>  Location: PIN_31,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- C_1KHZ_021	=>  Location: PIN_30,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- D_500HZ_021	=>  Location: PIN_32,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- S[1]	=>  Location: PIN_39,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- S[0]	=>  Location: PIN_137,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF lab2_fre_div3_021 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_B2_021 : std_logic;
SIGNAL ww_S : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_C_1KHZ_021 : std_logic;
SIGNAL ww_D_500HZ_021 : std_logic;
SIGNAL \B2_021~output_o\ : std_logic;
SIGNAL \D_500HZ_021~input_o\ : std_logic;
SIGNAL \C_1KHZ_021~input_o\ : std_logic;
SIGNAL \S[1]~input_o\ : std_logic;
SIGNAL \S[0]~input_o\ : std_logic;
SIGNAL \inst|sub|78~0_combout\ : std_logic;

BEGIN

B2_021 <= ww_B2_021;
ww_S <= S;
ww_C_1KHZ_021 <= C_1KHZ_021;
ww_D_500HZ_021 <= D_500HZ_021;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

-- Location: IOOBUF_X0_Y7_N2
\B2_021~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|sub|78~0_combout\,
	devoe => ww_devoe,
	o => \B2_021~output_o\);

-- Location: IOIBUF_X0_Y6_N15
\D_500HZ_021~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_D_500HZ_021,
	o => \D_500HZ_021~input_o\);

-- Location: IOIBUF_X0_Y8_N15
\C_1KHZ_021~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_C_1KHZ_021,
	o => \C_1KHZ_021~input_o\);

-- Location: IOIBUF_X1_Y0_N15
\S[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_S(1),
	o => \S[1]~input_o\);

-- Location: IOIBUF_X7_Y24_N1
\S[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_S(0),
	o => \S[0]~input_o\);

-- Location: LCCOMB_X1_Y19_N24
\inst|sub|78~0\ : cycloneive_lcell_comb
-- Equation(s):
-- \inst|sub|78~0_combout\ = (\S[1]~input_o\ & (\D_500HZ_021~input_o\ & ((!\S[0]~input_o\)))) # (!\S[1]~input_o\ & (((\C_1KHZ_021~input_o\ & \S[0]~input_o\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \D_500HZ_021~input_o\,
	datab => \C_1KHZ_021~input_o\,
	datac => \S[1]~input_o\,
	datad => \S[0]~input_o\,
	combout => \inst|sub|78~0_combout\);

ww_B2_021 <= \B2_021~output_o\;
END structure;


